Low turn-on voltage inp schottky device and method

ABSTRACT

A Schottky diode, and a method of making the same, which is fabricated on InP material and a Schottky layer including In x Al 1-x As with x&gt;0.6, or else including a chirped graded superlattice in which successive periods of the superlattice contain progressively less GaInAs and progressively more AlInAs, the increase in AlInAs being terminated before the proportion of AlInAs within the last period (adjacent the anode metal) exceeds 80%. Such fabrication creates an InP-based Schottky diode having a low turn-on voltage which may be predictably set within a range by adjusting the fabrication parameters.

FIELD OF THE INVENTION

[0001] The present invention pertains to Schottky diodes, and moreparticularly to Schottky diodes fabricated using InP semiconductormaterial.

BACKGROUND

[0002] Schottky diodes are well-known in GaAs and Si technologies. SomeSi-based Schottky diodes have fairly low turn-on voltages but sufferfrom high series resistance and relatively poor frequency response.Si-based Schottky diodes are not easily integrated into InP-basedsemiconductor fabrication.

[0003] Low turn-on voltages are often desirable for Schottky diodes,particularly for mixer applications. U.S. Pat. No. 5,665,999 issued Sep.9, 1997 to H. Brugger, teaches that low turn-on voltage Schottky diodespermit a low conversion loss without requiring a high pumping capacityin the local oscillator, and without using a bias voltage which may leadto Townsend current-hum disturbances. A GaAs Schottky device withreduced turn-on voltage is taught as fabricated using a gradedInGa_((1-x))As layer over a GaAs substrate, where the In content, x,increases continuously in the direction of the metal contact.Compatibility with InP is not taught, and the spatially varying latticemismatch created by this process is thought potentially unreliable withInP technologies.

[0004] Schottky diodes compatible with InP semiconductor technology areknown. For example, U.S. Pat. No. 5,652,435, issued Jul. 29, 1997 to E.Martin et al., describes a Schottky diode optical detector wherein thelight-sensitive InGaAs layer is cladded front and back with InAlAscurrent-blocking layers. This device has a relatively high turn-onvoltage similar to that of conventional GaAs Schottky diodes.

[0005] Some investigation into the relationship between Schottky barrierheight and the proportion of In in In_(x)Al_(1-x)As material on an InPsubstrate has been undertaken by C. L. Lin, et al. in “Compositiondependence of Au/In_(x)A_(1-x)As Schottky barrier heights,” AppliedPhysics Letters 49 (23), Dec. 8, 1986, pp. 1593-1595. Lin performs testson the noted compound for 0.45≦x≦0.55, a range producing relatively highSchottky barriers.

[0006] InP-compatible Schottky diodes using a graded superlatticeSchottky layer are also known. For example, U.S. Pat. No. 5,198,682issued Mar. 30, 1993 to C. -S. Wu et al. describes an infraredphotodetector using a superlattice having a graded dopant concentration,thereby developing an internal field which aids in the collection ofphotoexcited carriers. Lee et al., in Appl. Phys. Lett. Vol. 54, May1989, pp. 1863-1865, teaches use of a graded superlattice ofInGaAs/InAlAs to obtain enhanced Schottky barrier height. U.S. Pat. No.5,572,043, issued Nov. 5, 1996 to Shimizu et al. describes anotherSL-based Schottky diode, using sublayers of variously lattice-mismatchedcompounds and alternating compressively and tensilely strained layers tobalance the mismatches. Each of these three references describe Schottkydiodes having a relatively high turn-on voltage of 0.6V -0.7V.

[0007] InP-compatible Schottky diodes having high turn-on voltages areknown. For example, U.S. Pat. No. 4,471,367 issued Sep. 11, 1984 to C.Chen et al. discloses a MESFET-gate Schottky structure composed of athin, heavily doped InGaAs layer overlying a layer of low-doped InGaAshaving an increased barrier height. Another example is U.S. Pat. No.4,954,851, issued Sep. 4, 1990 to W. Chan, which describes a Schottkydiode with a cadmium-containing layer overlying an InAlAs layer. TheCd-containing layer enhances the barrier height of the diode.

[0008] Thus, Schottky diodes with reduced turn-on voltages exist but arenot known to be compatible with InP-based fabrication techniques.Schottky diodes compatible witn InP are known, but all have conventionalor high turn-on voltages. Yet, InP-based fabrication technologies aredesirable, and low turn-on voltage Schottky diodes are particularlyuseful in certain applications, such as high-frequency mixers. A needtherefore exists for low turn-on voltage Schottky diodes, and a methodof making the same, which are compatible with InP fabricationtechnologies.

SUMMARY OF THE INVENTION

[0009] The present invention addresses the need for low turn-on voltageSchottky diodes compatible with InP-based fabrication by employing anInP lattice-compatible Schottky layer which interfaces with the Schottkymetal layer and provides a relatively low Schottky barrier heightresulting in a low turn-on voltage.

[0010] The Schottky metal layer is preferably Ti/Pt/Au. The Schottkylayer is preferably grown over a low-doped GaInAs layer, which in turnis preferably grown over a highly doped GaInAs layer. The highly-dopedGaInAs layer forms the Schottky cathode contact. The cathode contact isgrown over a buffer layer, such as 2500 A of AlInAs or 100 A of undopedGaInAs, preferably grown directly on the InP substrate.

[0011] According to the present invention, the Schottky layer isprocessed to produce a low turn-on voltage.

[0012] According to a first embodiment of the invention, the Schottkylayer includes strained Al_((1-x))In_(x) As, and for x=0.70 produces aturn-on voltage of 0.25V @ImA. The corresponding 0.3 Al content is lowerthan that which lattice-matches InP, and accordingly the thickness ofthe layer is preferably around 100 Å to limit effects from the strain.

[0013] According to second, third and fourth embodiments of theinvention, the Schottky layer includes a chirped superlattice composedof a plurality of periods, each period containing sublayers of Ga_(0.47)In_(0.53)As and Al_(0.48) In_(0.52)As, which are lattice-matched to InP.The proportional thickness of the two compounds is varied from period toperiod to provide a step-wise, or chirped, grade in composition of thesuperlattice from GaInAs toward AlInAs. The turn-on voltage can beprecisely controlled by truncating the grading steps before completing atransition to predominantly AlInAs.

[0014] Throughout this patent, GaInAs refers to Ga_(0.47)In_(0.53)As,and AlInAs refers to Al_(0.48)In_(0.52)As, unless a differentcomposition is specified.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015]FIG. 1 is the layer structure of a diode according to the presentinvention after a first etch.

[0016]FIG. 2 shows the structure of the diode after a second etch step.

[0017]FIG. 3 shows the structure of the diode after a third etch step.

[0018]FIG. 4 shows the structure of the diode after passivation andetching of the passivation layer.

[0019]FIG. 5 shows the structure of the completed diode.

[0020]FIG. 6 depicts a chirped graded superlattice having nine periods.

[0021]FIG. 7 depicts the Schottky layer structure for the secondembodiment of the present invention.

[0022]FIG. 8 depicts the Schottky layer structure for the thirdembodiment of the present invention.

[0023]FIG. 9 depicts the Schottky layer structure for the fourthembodiment of the present invention.

[0024]FIG. 10 shows I-V curves for three embodiments of the presentinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] While discrete Schottky diodes can be made according to thepresent invention, the present invention is very well suited tointegrated fabrication. Such fabrication, as shown in FIG. 1, preferablyuses Molecular Beam Epitaxy (MBE) to grow each of the layers on InPsubstrate 1, though any other compatible process, such as Metal OrganicVapor Phase Epitaxy(MOVPE), may be used. Buffer layer 3 is growndirectly on InP substrate 1. Buffer layer 3 is about 2500 Å of undopedAlInAs, or may alternatively be about 100 Å of undoped GaInAs. Cathodecontact layer 5 is grown on the buffer layer, preferably highly doped,preferably with Si, to n=1×10¹⁹ cm⁻³. Cathode contact layer 5 ispreferably grown to about 3000 Å of GaInAs, the thickness helping toreduce bulk resistance of the cathode and also simplifying the lateretch step down to cathode contact layer 5 which permits deposition ofcathode contact 21 (FIG. 2). Depletion layer 7 is about 1000 Å ofundoped GaInAs grown atop cathode contact layer, and helps to minimizethe diode capacitance by increasing the depletion width of the diode.

[0026] Schottky layer 9 is grown next. In a first embodiment of theinvention the Schottky layer is undoped, strained Al_(1-x)In_(x)As,preferably Al_(0.3)In_(0.7)As. In this first embodiment, Schottky layer9 is preferably grown to about 100 Å thick to reduce crystal anomaliesdue to the strain from the lattice mismatch. Schottky layer 9 isdescribed further below in accordance with second, third and fourthalternative embodiments of the invention.

[0027] After Schottky layer 9, a cap layer of about 50 Å of undopedGaInAs (not shown) is grown to protect AlInAs in the Schottky layer fromambient oxygen. FIG. 1 shows the device after the first etch step hasremoved the cap, and Schottky metal layer 10 has been deposited by anystandard technique. Schottky metal layer 10 is preferably about 250 ÅTi, 1000 Å Pt, and 6000 Å Au.

[0028] An etch step, preferably using Schottky metal 10 as an etch stop,mesa etches Schottky layer 9 and depletion layer 7 to expose cathodecontact layer 5 as shown in FIG. 2. Due to the thickness of cathodecontact layer 5, a timed wet etch may be used, or any compatible etchprocess. Next, cathode ohmic contact 21 is deposited on cathode contactlayer 5, preferably with 900 Å AuGe, 100 Å Ni, and 2000 Å Au.

[0029]FIG. 3 shows the result of the next two steps. Cathode contactlayer 5 and depletion layer 3 are both mesa-etched using any compatibleetch technique, to isolate the diode structure on substrate 1.Thereafter, first level interconnect metal 31 is deposited, using anycompatible metal, to provide means for connecting external circuits tothe device.

[0030]FIG. 4 shows the device after the step of adding passivation layer41 of preferably silicon nitride, and after the subsequent step ofetching passivation layer 41 to expose Schottky metal 10 and first layermetallization 31.

[0031]FIG. 5 shows airbridge 51 placed to connect Schottky anode metal10 to first layer metallization 31. Airbridge 51 is preferred for highfrequency applications, as it reduces diode capacitance. In manyapplications, the anode may be connected by other well-knownmetallization techniques.

[0032]FIG. 6 shows the layer structure of a superlattice composed ofnine periods 61-69 which are each compound of first sublayer 60 andsecond sublayer 70. Such a superlattice may be used to grade a materialin a stepwise or “chirped” fashion, from predominantly the material ofsecond sublayer 70 in first period 61, to predominantly the material offirst sublayer 60. Between successive periods, the thickness of firstsublayer 60 is increased, while the thickness of second sublayer 70 iscorrespondingly decreased. For convenience, first sublayer 60 is about10% of the thickness of first period 61 of a nine-period chirped gradedsuperlattice, increasing linearly to 90% of the thickness of ninthperiod 69; while second sublayer 70 is about 90% of the thickness offirst period 61, reducing to about 10% of the thickness of ninth period69.

[0033]FIG. 7 shows Schottky layer 9 according to a second embodiment ofthe present invention. For convenience, periods 71-77 are each about 33Å thick. First sublayers 78 are AlInAs, and second sublayers 79 areGaInAs, both lattice-matched to InP. In first period 71, first sublayer78 is about 3.3 Å thick; subsequent sublayers 78 increase by about 3.3 Åin each successive period so that in seventh period 77, first sublayer78 is about 23.1 Å thick. Second sublayer 79 decreases by about 3.3 Åper period from about 29.7 Å in first period 71 to about 9.9 Å inseventh period 77. Thus, FIG. 7 shows a chirped graded superlatticebased on a nine-period grading transition, but truncated at sevenperiods. A Schottky diode fabricated according to this embodimentresults in a room-temperature turn-on voltage of about 0.37V at 1 mA.I-V curve 700 of FIG. 10 is for this embodiment of the invention.

[0034]FIG. 8 shows the layer structure of Schottky layer 9 according toa third embodiment of the present invention. This embodiment is alsobased on a nine-period superlattice grading arrangement, but istruncated at 5 layers instead of at 7. First sublayer 88 of first period81 is about 3.3 Å of AlInAs, increasing by about 3.3 Å in successiveperiods 82, 83, 84 and 85 so that in fifth period 85 it is about 16.5 Å.Second sublayer 89 is GaInAs, and is about 29.7 Å in first period 81,decreasing to about 16.5 Å in fifth period 85. A Schottky diodefabricated according to this embodiment results in a room-temperatureturn-on voltage of about 0.25V at 1 mA. I-V curve 800 of FIG. 10 is forthis embodiment of the invention.

[0035]FIG. 9 shows the layer structure of Schottky layer 9 according toa fourth embodiment of the present invention. This embodiment is alsobased on a nine-period superlattice grading arrangement, but istruncated at 3 layers instead of at 5 or 7. First sublayer 98 of firstperiod 91 is about 3.3 Å of AlInAs, increasing by about 3.3 Å insuccessive periods 92 and 93 so that in third period 93 it is about 10Å. Second sublayer 99 is GaInAs, and is about 29.7 Å in first period 91,decreasing to about 23 Å in third period 93. A Schottky diode fabricatedaccording to this embodiment results in a room-temperature turn-onvoltage of about 0.15V at 1 mA. I-V curve 900 of FIG. 10 is for thisembodiment of the invention.

[0036]FIG. 10 shows an I-V curve for each of three describedembodiments. Curve 700 is the IV curve for the embodiment of FIG. 7,curve 800 for the embodiment of FIG. 8 (below), and curve 900 for theembodiment of FIG. 9 (below).

[0037] For sufficiently thin periods, the effective bandgap tracks theaverage composition of the superlaffice. Since the superlattice of thesecond, third and fourth embodiments of the invention is chirped, theSchottky barrier height changes discontinuously from period to period.Small chirped grading steps produce smaller Schottky barrier heightdiscontinuities, and hence are thought to help reduce carrier pile-upwhich may occur on Schottky barrier height discontinuities. Since suchpile-up may reduce speed, smaller grading steps may thus enhance speed.Accordingly, the present invention could be practiced with asuperlattice truncated partway through a GaInAs to AlInAs gradingarrangement which requires more than nine periods to complete, andcorrespondingly has smaller steps from period to period.

[0038] Embodiments of the present invention have been described whichtruncate a nine-period grading arrangement at three, five and sevenperiods. Truncating at different numbers of periods permits closecontrol of the turn-on voltage of Schottky diodes fabricated accordingto the present invention. If truncation is based upon gradingarrangements requiring more than nine periods to completion, theon-voltage step size between different truncation points iscorrespondingly reduced, enhancing the fineness of fabrication controlof that parameter.

[0039] Periods of different, and indeed varying, thickness are withincontemplation of the present invention. The composition of sublayersneed not change in equal-sized steps between successive periods. Periodsmay have sublayers of alternative materials, and may have additionalmaterials added.

[0040] Fabrication details are merely exemplary; the invention isdefined by the following claims.

What is claimed is:
 1. A Schottky diode comprising a cathode contact layer and a semiconductor Schottky layer adjacent a Schottky anode metallization, wherein said Schottky layer is a superlattice having a plurality of layer periods from a first layer period nearest the cathode contact layer to a last layer period nearest the anode metallization, each layer period having a thickness and including a first sublayer of GaInAs having a thickness and a second sublayer of AlinAs having a thickness, and each layer period having a proportion of GaInAs to AlInAs; and wherein the thickness of the first and second sublayers is varied between adjacent layer periods such that the proportion of GaInAs to AlInAs varies stepwise between adjacent layer periods, and the thickness of AlInAs in said last layer period is less than 80% of the thickness of said last layer period.
 2. A Schottky diode according to claim 1 wherein each layer period is composed of said first and second sublayers, and said first and second sublayers are lattice-matched to InP.
 3. A Schottky diode according to claim 1 wherein the thicknesses of the first sublayers and of the second sublayers are varied in opposite directions to vary the proportions of GaInAs to AlInAs by a similar amount between each successive adjacent layer period from the first layer period to the last layer period.
 4. A Schottky diode according to claim 1 wherein the Schottky anode metallization of the device is connected via an airbridge to metallization for interconnection to external circuitry.
 5. A Schottky diode according to claim 3 wherein within the first layer period the first sublayer thickness is about 10% of the first layer period thickness and the second sublayer thickness is about 90% of the first layer period thickness, and within the last layer period the first sublayer thickness is about 30% of a last layer period thickness and the second sublayer thickness is about 70% of the last layer period thickness.
 6. A Schottky diode according to claim 1 wherein within the first layer period the first sublayer thickness is about 10% of a first layer period thickness and the second sublayer thickness is about 90% of the first layer period thickness, and within the last layer period the first sublayer thickness is about 50% of the last layer period thickness.
 7. A Schottky diode according to claim 3 wherein within the first layer period the first sublayer thickness is about 10% of the first layer period thickness and the second sublayer thickness is about 90% of the first layer period thickness, and within the last layer period the first sublayer thickness is about 70% of a last layer period thickness and the second sublayer thickness is about 30% of the last layer period thickness.
 8. A Schottky diode according to claim 3 wherein layer periods are composed of sublayers of GaInAs lattice-matched to InP and AlInAs lattice-matticed to InP.
 9. A Schottky diode comprising: an InP substrate; a Schottky anode metallization; and a semicondoctor Schottky layer adjacent the Schottky anode metallization, wherein said Schottky layer is predominantly In_(x)Al_(1-x)As with x greater than 0.6.
 10. A Schottky diode according to claim 9 wherein said Schottky anode metallization device is connected through an airbridge to metallization for interconnection to external circuitry.
 11. A Schottky diode according to claim 9 wherein x is about 0.7.
 12. A method of making a Schottky diode comprising steps of: preparing an InP substrate; growing a doped cathode contact layer of GaInAs above the substrate; growing a semiconductor Schottky layer above the cathode contact layer, the Schottky layer being either: (a) a truncated chirped superlattice of GaInAs and AlIAs, or (b) predominantly In_(x)Al_(1-x)As with x greater than 0.6; and depositing a metal anode contact of the Schottky layer.
 13. The method of claim 12 wherein the GaInAs and the AlInAs are lattice-matched to InP.
 14. The method of claim 12 wherein the Schottky layer is a truncated chirped superlattice, and the step of growing the Schottky layer includes the steps of: growing a plurality of layer periods including a first layer period nearest the cathode contact layer and a last layer period nearest the metal anode contact, each layer period having a thickness, and each layer period including as constituents a first sublayer of AlInAs having a thickness and a second sublayer of GaInAs having a thickness, the AlInAs in each layer period being a proportion of a total of material composing that layer period; wherein the thicknesses of the first sublayers of each layer period are varied for successive layer periods and the thicknesses of the second sublayers of each layer period are varied for successive layer periods to stepwise change the proportion of AlInAs to the total material of successive layer periods, and truncating growth of further layer periods such that the proportion of AlInAs in the last layer period grown does not exceed 80% of the total material of the last layer period.
 15. The method of claim 14 wherein the first sublayer of each layer period is grown with increasing thickness in each successive layer period; and the second sublayer of each layer period is grown with decreasing thickness in each successive layer period; such that the proportion of AlInAs increases stepwise for each successive layer period.
 16. The method of claim 15 wherein the stepwise increase in the proportion of AlInAs is approximately uniform for each successive layer period.
 17. The method of claim 16 wherein the proportion of AlInAs of the last layer period does not exceed 60% of the total material of the last layer period.
 18. The method of claim 14 wherein the number of layer periods is five.
 19. The method of claim 14 wherein the superlatice is composed of AlInAs lattice-matched to InP and GaInAs lattice-matched to InP, and the proportion of AlInAs of the last layer period is between 30% and 70% of the total material of the last layer period.
 20. The method of claim 19 wherein the proportion of AlInAs in the last layer period is about 50% of the total material of the last layer period. 